In recent years, with reduction of a chip size, a PN element isolation width within an SRAM cell is reduced. As a result, the capability of a parasitic bipolar transistor is improved, so that it becomes easy to enter into a latch up state in a memory cell. In order to enter into a latch up, trigger current is necessary. However, with miniaturization of the memory cell, electrical charges caused by deterioration in SER (Soft Error Rate) immunity tend to be generated. As a measure against this, it has become a general practice to form and dispose a subcontact or a well contact for every several to several tens of memory cells, and to fix P wells at a VSS potential and fix N wells at a VDD potential. However, it is necessary to secure a region for disposing subcontacts or well contacts in addition to the region of the memory cells, thereby leading to an increase in the chip size.
In order to cope with the problem as described above, implantation of P+ impurity ions or N+ impurity ions that have the same conductive type as that of a well into a portion of an N+ diffusion layer that constitutes the source/drain of an N-type MOS transistor in an SRAM memory cell or a portion of a P+ diffusion layer that constitutes the source/drain of a P-type MOS transistor in the SRAM memory cell is performed, thereby forming a so-called Butted diffusion layer. Then, via the Butted diffusion layer, the well is fixed at a predetermined potential. Assume an N-type MOS transistor in which a P well 201 and an element isolation film (STI) 203 are formed in a silicon substrate 200, a gate insulating film 204 and a gate electrode 205 are formed over the element isolation film 203, and an N-type source/drain region 210 constituted from an N− diffusion layer 211 and an N+ diffusion layer 212 is formed in the P-well 201, as illustrated in FIG. 16, for example. When a GND contact (contact hall) 230 for supplying the VSS potential or a GND potential herein to the P-well 201 is configured, a P-type impurity is implanted into a portion of the N+ diffusion layer 212 in a high concentration, thereby forming a P+ diffusion layer 231 as a Butted diffusion layer. Then, via this P+ diffusion layer 231, power supply to the P-well 201 is performed. Incidentally, reference numeral 206 denotes sidewalls, reference numeral 207 denotes a silicide layer, and reference numeral 208 denotes an inter-layer film. In this structure, via the contact 230 and the Butted diffusion layer 231, the P-well can be fixed at the GND potential from metal wiring for supplying the GND potential fundamentally necessary for the memory cell. Further, via the contact hole and the Butted diffusion layer, an N-well region can be fixed at the VDD potential output from metal wiring for supplying the VDD potential fundamentally necessary for the memory cell. Thus, without increasing the well contact regions between the memory cells by design, deterioration of latch-up immunity can be prevented without increase in the area of the memory cell due to addition of wiring and connection hole(s) in the memory cell.
In order to form this Butted diffusion layer, however, it is necessary to form in a high-concentration N+ diffusion layer or high-concentration P+ diffusion layer the P+ diffusion layer or the N+ diffusion layer of an opposite conductivity type, respectively, by implantation of high-concentration ions, as described before. Thus, the process for this becomes difficult. When the Butted diffusion layer is formed by implanting into a portion of the N+ diffusion layer the P-type impurity ions of the same conductivity type as that of the well as described above, it is difficult to change the conductivity of the N+ diffusion layer having a concentration of 1E18/cm2 or higher, for example, which is present in the vicinity of the surface of the substrate as indicated by a result of a process simulation in FIG. 17, by implantation of a high dose of the P-type impurity ions.
On contrast therewith, in the technique disclosed in Patent Document 1, a portion of the N−type source/drain region 210 is formed to be shallow using the N− diffusion layer 211 alone, as shown in FIG. 18. Then, at least a portion of the silicide layer 207 formed on the N− diffusion layer 211 that constitutes the N-type source/drain region 210 or the N+ diffusion layer 212 is formed to be deep to reach the P-well 201. Then, the P-well is fixed at the GND potential through the silicide layer 207. In the technique in this Patent Document 1, it is not necessary to change the conductivity of a high-concentration diffusion layer into the opposite conductivity type by ion implantation. Thus, it is advantageous in that manufacture of contacts becomes facilitated.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2004-47933A